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DS2141A T1 Controller
www.dalsemi.com
FEATURES
DS1/ISDN-PRI framing transceiver Frames to D4, ESF, and SLC-96 formats Parallel control port Onboard, dual two-frame elastic store slip buffers Extracts and inserts robbed-bit signaling Programmable output clocks Onboard FDL support circuitry 5V supply; low-power CMOS Available in 40-pin DIP and 44-pin PLCC (DS2141Q) Compatible with DS2186 Transmit Line Interface, DS2187 Receive Line Interface, DS2188 Jitter Attenuator, DS2290 T1 Isolation Stik, and DS2291 T1 Long Loop Stik
PIN ASSIGNMENT
TCLK TSER TCHCLK TPOS TNEG AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 BTS RD(DS) CS ALE(AS) WR(R/W) RLINK VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD TSYNC TLINK TLCLK INT1 INT2 RLOS/LOTC TCHBLK RCHBLK LI CS LI CLK LI SDI SYSCLK RNEG RPOS RSYNC RSER RCHCLK RCLK RLCLK
40-Pin DIP (600-mil)
TNEG TPOS TCHCLK TSER TCLK VDD TSYNC TLINK TLCLK INT1 INT2 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 BTS RD(DS) NC
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35
44-PIN PLCC
34 33 32 31 30 29 28
RLOS/LOTC TCHBLK RCHBLK LI_CS LI_CLK LI_SDI NC NC SYSCLK RNEG RPOS
DESCRIPTION
The DS2141A is a comprehensive, software-driven T1 framer. It is meant to act as a slave or coprocessor to a microcontroller or microprocessor. Quick access via the parallel control port allows a single micro to handle many T1 lines. The DS2141A is very flexible and can be configured into numerous orientations via software. The software orientation of the device allows the user to modify their design to conform to future T1 specification changes. The controller contains a set of 62 8-bit internal registers which the user can access. These internal registers are used to configure the device and obtain information from the T1 1 of 39 112099
NC CS ALE(AS) WR(R/W) RLINK VSS RLCLK RCLK RCHCLK RSER RSYNC
DS2141A
link. The device fully meets all of the latest T1 specifications including ANSI T1.403-1989, AT&T TR 62411 (12-90), and CCITT G.704 and G.706.
1.0 INTRODUCTION
The DS2141A T1 Controller has four main sections: the receive side, the transmit side, the line interface controller, and the parallel control port. See the block diagram below. On the receive side, the device will clock in the serial T1 stream via the RPOS and RNEG pins. The synchronizer will locate the frame and multiframe patterns and establish their respective positions. This information will be used by the rest of the receive side circuitry. The DS2141A is an "off-line" framer, which means that all of the T1 serial stream that goes into the device will come out of it unchanged. Once the T1 data has been framed to, the robbed-bit signaling data and FDL can be extracted. The 2-frame elastic stores can either be enabled or bypassed. The transmit side clocks in the unframed T1 stream at TSER and adds in the framing pattern, the robbedbit signaling, and the FDL. The line interface control port will update line interface devices that contain a serial port. The parallel control port contains a multiplexed address and data structure which can be connected to either a microcontroller or microprocessor.
DS2141A BLOCK DIAGRAM
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DS2141A
DS2141A FEATURES
Parallel control port Large error counters Onboard dual 2-frame elastic store FDL support circuitry Robbed-bit signaling extraction and insertion Programmable output clocks Fully independent transmit and receive sections Frame sync generation Error-tolerant yellow and blue alarm detection Output pin test mode Payload loopback capability SLC-96 support Remote loop up/down code detection Loss of transmit clock detection Loss of receive clock detection 1's density violation detection
PIN DESCRIPTION Table 1
PIN 1 2 3 SYMBOL TCLK TSER TCHCLK TYPE DESCRIPTION I Transmit Clock. 1.544 MHz primary clock. I Transmit Serial Data. Transmit NRZ serial data, sampled on the falling edge of TCLK. O Transmit Channel Clock. 192 kHz clock which pulses high during the LSB of each channel. Useful for parallel-to-serial conversion of channel data, locating robbed-bit signaling bits, and for blocking clocks in DDS applications. See Section 13 for timing details. O Transmit Bipolar Data. Updated on rising edge of TCLK. I/O I Address/Data Bus. An 8-bit multiplexed address/data bus. Bus Type Select. Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of RD (DS), ALE(AS), and WR (R/ W ) pins. If BTS=1, then these pins assume the function listed in parentheses (). Read Input (Data Strobe). Chip Select. Must be low to read or write the port. Address Latch Enable (Address Strobe). A positive-going edge serves to demultiplex the bus. Write Input (Read/Write). Receive Link Data. Updated with either FDL data (ESF) or Fs-bits (D4) or Z-bits (ZBTSI) one RCLK before the start of a frame. See Section 13 for timing details. Signal Ground. 0.0 volts. Receive Link Clock. 192 kHz clock which pulses high during the LSB of each channel. Useful for parallel-to-serial conversion of channel data, locating robbed-bit signaling bits, and for blocking clocks in DDS applications. See Section 13 for timing details. Receive Clock. 1.544 MHz primary clock. 3 of 39
4 5 6-13 14
TPOS TNEG AD0-AD7 BTS
15 16 17 18 19
RD (DS)
CS ALE(AS)
WR (R/ W )
I I I I O
RLINK
20 21
VSS RLCLK
O
22
RCLK
I
DS2141A
PIN 23
SYMBOL RCHCLK
24 25
RSER RSYNC
26 27 28
RPOS RNEG SYSCLK
29 30 31 32 33
LI_SDI LI_CLK
LI_CS
RCHBLK TCHBLK
34
RLOS/LOTC
35 36
INT2 INT1
37
TLCLK
TYPE DESCRIPTION O Receive Channel Clock. 192 kHz clock which pulses high during the LSB of each channel. Useful for parallel-to-serial conversion of channel data, locating robbed-bit signaling bits, and for blocking clocks in DDS applications. See Section 13 for timing details. O Receive Serial Data. Received NRZ serial data; updated on rising edges of RCLK. I/O Receive Sync. An extracted pulse, one RCLK wide, is output at this pin which identifies either frame (RCR2.4=0) or multiframe boundaries (RCR2.4=1). If set to output frame boundaries, then via RCR2.5, RSYNC can also be set to output double-wide pulses on signaling frames. If the elastic store is enabled via the CCR1.2, then this pin can be enabled to be an input via RCR2.3 at which a frame boundary pulse is applied. See Section 13 for timing details. I Receive Bipolar Data Inputs. Sampled on falling edge of RCLK. Tie together to receive NRZ data and disable bipolar violation monitoring circuitry. I System Clock. 1.544 MHz or 2.048 MHz clock. Only used when the elastic store function is enabled via the CCR. Should be tied low in applications that do not use the elastic store. O Serial Port Data for the Line Interface. Connects directly to the SDI input pin on the line interface. O Serial Port Clock for the Line Interface. Connects directly to the SCLK input pin on the line interface. O Serial Port Chip Select for the Line Interface. Connects directly to the CS input pin on the line interface. O Receive/Transmit Channel Block. A user-programmable output that can be forced high or low during any of the 24 T1 channels. Useful for blocking clocks to a serial UART or LAPD controller in application where not all T1 channels are used such as Fractional T1, 384K bps service, 768K bps, or ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications. See Section 13 for timing details. O Receive Loss of Sync/Loss of Transmit Clock. A dual function output. If CCR1.6=0, then this pin will toggle high when the synchronizer is searching for the T1 frame and multiframe. If CCR1.6=1, then this pin will toggle high when the TCLK pin has not been toggled for 5 ms. O Receive Alarm Interrupt 2. Flags host controller during conditions defined in Status Register 2. Active low, open drain output. O Receive Alarm Interrupt 1. Flags host controller during alarm conditions defined in Status Register 1. Active low, open drain output. O Transmit Link Clock. 4 kHz or 2 kHz (ZBTSI) demand clock for the TLINK input. See Section 13 for timing details.
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DS2141A
PIN 38
SYMBOL TLINK
39
TSYNC
40
VDD
TYPE DESCRIPTION I Transmit Link Data. If enabled via TCR1.2, this pin will be sampled during the F-bit time on the falling edge of TCLK for data insertion into either the FDL stream (ESF) or the Fs-bit position (D4) or the Z-bit position (ZBTSI). See Section 13 for timing details. I/O Transmit Sync. A pulse at this pin will establish either frame or multiframe boundaries for the DS2141A. Via TCR2.2, the DS2141A can be programmed to output either a frame or multiframe pulse at this pin. If this pin is set to output pulses at frame boundaries, it can also be set via TCR2.4 to output double-wide pulses at signaling frames. See Section 13 for timing details. Positive Supply. 5.0 volts.
DS2141A REGISTER MAP
ADDRESS R/W REGISTER NAME 20 R/W Status Register 1 21 R/W Status Register 2 22 R/W Receive Information Register 23 R Bipolar Violation/ESF Error Event Count Register 1 24 R Bipolar Violation/ESF Error Event Count Register 2 25 R CRC6 Count Register 1 26 R CRC6 Count Register 2 27 R Frame Error Count Register 28 R Receive FDL Register 29 R/W Receive FDL Match Register 1 2A R/W Receive FDL Match Register 2 2B R/W Receive Control Register 1 2C R/W Receive Control Register 2 2D R/W Receive Mark Register 1 2E R/W Receive Mark Register 2 2F R/W Receive Mark Register 3 30 Not Assigned 31 Not Assigned 32 R/W Transmit Channel Blocking Register 1 33 R/W Transmit Channel Blocking Register 2 5 of 39 ADDRESS R/W REGISTER NAME 34 R/W Transmit Channel Blocking Register 3 35 R/W Transmit Control Register 1 36 R/W Transmit Control Register 2 37 R/W Common Control Register 1 38 R/W Common Control Register 2 39 R/W Transmit Transparency Register 1 3A R/W Transmit Transparency Register 2 3B R/W Transmit Transparency Register 3 3C R/W Transmit Idle Register 1 3D R/W Transmit Idle Register 2 3E R/W Transmit Idle Register 3 3F R/W Transmit Idle Definition Register 60 R Receive Signaling Register 1 61 R Receive Signaling Register 2 62 R Receive Signaling Register 3 63 R Receive Signaling Register 4 64 R Receive Signaling Register 5
DS2141A
ADDRESS R/W REGISTER NAME 65 R Receive Signaling Register 6 66 R Receive Signaling Register 7 67 R Receive Signaling Register 8 68 R Receive Signaling Register 9 69 R Receive Signaling Register 10 6A R Receive Signaling Register 11 6B R Receive Signaling Register 12 6C R/W Receive Channel Blocking Register 1 6D R/W Receive Channel Blocking Register 2 6E R/W Receive Channel Blocking Register 3 6F R/W Interrupt Mask Register 2 70 R/W Transmit Signaling Register 1 71 R/W Transmit Signaling Register 2 72 R/W Transmit Signaling Register 3
ADDRESS R/W REGISTER NAME 73 R/W Transmit Signaling Register 4 74 R/W Transmit Signaling Register 5 75 R/W Transmit Signaling Register 6 76 R/W Transmit Signaling Register 7 77 R/W Transmit Signaling Register 8 78 R/W Transmit Signaling Register 9 79 R/W Transmit Signaling Register 10 7A R/W Transmit Signaling Register 11 7B R/W Transmit Signaling Register 12 7C R/W LI Control Register Byte 1 7D R/W LI Control Register Byte 2 7E R/W Transmit FDL Register 7F R/W Interrupt Mask Register 1 Note: All values indicated within the Address column are hexadecimal.
2.0 PARALLEL PORT
The DS2141A is controlled via a multiplexed bidirectional address/data bus by an external microcontroller or microprocessor. The DS2141A can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams in the AC Electrical Characteristics for more details. The multiplexed bus on the DS2141A saves pins because the address information and data information share the same signal paths. The addresses are presented to the pins in the first portion of the bus cycle and data will be transferred on the pins during second portion of the bus cycle. Addresses must be valid prior to the falling edge of ALE(AS), at which time the DS2141A latches the address from the AD0 to AD7 pins. Valid write data must be present and held stable during the later portion of the DS or WR pulses. In a read cycle, the DS2141A outputs a byte of data during the latter portion of the DS or RD pulses. The read cycle is terminated and the bus returns to a high impedance state as RD transitions high in Intel timing or as DS transitions low in Motorola timing.
3.0 CONTROL REGISTERS
The operation of the DS2141A is configured via a set of six registers. Typically, the control registers are only accessed when the system is first powered up. Once, the DS2141A has been initialized, the control registers will only need to be accessed when there is a change in the system configuration. There are two Receive Control Registers (RCR1 and RCR2), two Transmit Control Registers (TCR1 and TCR2), and two Common Control Registers (CCR1 and CCR2). Each of the six registers is described below. 6 of 39
DS2141A
RCR1: RECEIVE CONTROL REGISTER 1 (2Bh)
(MSB) ARC OOF1 POSITION RCR1.7 RCR1.6 OOF2 SYNCC SYNCT SYNCE (LSB) RESYNC
SYMBOL ARC
NAME AND DESCRIPTION Not Assigned. Should be set to 0 when written to. Auto Resync Criteria. 0=Resync on OOF or RCL event. 1=Resync on OOF only. Out Of Frame Select 1. 0=2/4 frame bits in error. 1=2/5 frame bits in error. Out Of Frame Select 2. 0=follow RCR1.5. 1=2/6 frame bits in error. Sync Criteria. In D4 Framing Mode. 0=search for Ft pattern, then search for Fs pattern. 1=cross couple Ft and Fs pattern. In ESF Framing Mode. 0=search for FPS pattern only. 1=search for FPS and verify with CRC6. Sync Time. 0=qualify 10 bits. 1=qualify 24 bits. Sync Enable. 0=auto resync enabled. 1=auto resync disabled. Resync. When toggled from low to high, a resync is initiated. Must be cleared and set again for a subsequent resync.
OOF1
RCR1.5
OOF2
RCR1.4
SYNCC
RCR1.3
SYNCT
RCR1.2
SYNCE
RCR1.1
RESYNC
RCR1.0
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DS2141A
RCR2: RECEIVE CONTROL REGISTER 2 (2Ch)
(MSB) RCS RZBTSI RSDW RSM RSIO RD4YM FSBE (LSB) BPVCRS
SYMBOL RCS
POSITION RCR2.7
NAME AND DESCRIPTION Receive Code Select. 0=idle code (7F Hex). 1=digital milliwatt code (1E/0B/0B/1E/9E/8B/8B/9E Hex). Receive Side ZBTSI Enable. 0=ZBTSI disabled. 1=ZBTSI enabled. RSYNC Double-Wide. 0=do not pulse double-wide in signaling frames. 1=do pulse double-wide in signaling frames. (note: this bit must be set to 0 when RCR2.4 = 1 or when RCR2.3 = 1). RSYNC Mode Select. 0=frame mode (see the timing in Section 13). 1=multiframe mode (see the timing in Section 13). RSYNC I/O Select. 0=RSYNC is an output. 1=RSYNC is an input (only valid if elastic store enabled). (note: this bit must be set to 0 when CCR1.2 = 0). Receive Side D4 Yellow Alarm Select. 0=0 in bit 2 of all channels. 1=a 1 in the S-bit position of frame 12. Fs-Bit Error Report Enable. 0=do not report bit errors in the Fs-bit position in FECR. 1=report bit errors in the Fs-bit position in FECR. BPVCRS Function Select. 0=counts bipolar violations. 1=counts ESF error events (CRC6 OR 'ed with RLOS).
RZBTSI
RCR2.6
RSDW
RCR2.5
RSM
RCR2.4
RSIO
RCR2.3
RD4YM
RCR2.2
FSBE
RCR2.1
BPVCRS
RCR2.0
8 of 39
DS2141A
TCR1: TRANSMIT CONTROL REGISTER 1 (35h)
(MSB) ODF TFPT TCPT POSITION TCR1.7 RBSE GB7S TLINK TBL (LSB) TYEL
SYMBOL ODF
NAME AND DESCRIPTION Output Data Format. 0=bipolar data at TPOS and TNEG. 1=NRZ data at TPOS; TNEG = 0. Transmit Framing Pass Through. 0=Ft or FPS bits sourced internally. 1=Ft or FPS bits sampled at TSER during F-bit time. Transmit CRC Pass Through. 0=source CRC6 bits internally. 1=CRC6 bits sampled at TSER during F-bit time. Robbed Bit Signaling Enable. 0=no signaling is inserted in any channel. 1=signaling is inserted in all channels (the TTR registers can be used to block insertion on a channel by channel basis). Global Bit 7 Stuffing. 0=allow the TTR registers to determine which channels containing all zeros are to be bit 7 stuffed. 1=force bit 7 stuffing in all zero byte channels regardless of how the TTR registers are programmed. TLINK Select. 0=source FDL or Fs bits from TFDL register. 1=source FDL or Fs bits from the TLINK pin. Transmit Blue Alarm. 0=transmit data normally. 1=transmit an unframed all 1's code at TPOS and TNEG. Transmit Yellow Alarm. 0=do not transmit yellow alarm. 1=transmit yellow alarm.
TFPT
TCR1.6
TCPT
TCR1.5
RBSE
TCR1.4
GB7S
TCR1.3
TLINK
TCR1.2
TBL
TCR1.1
TYEL
TCR1.0
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DS2141A
TCR2: TRANSMIT CONTROL REGISTER 2 (36h)
(MSB) TESTM TESTIO TZBTSI TSDW TSM TSIO TD4YM (LSB) B7ZS
SYMBOL TESTM
POSITION TCR2.7
NAME AND DESCRIPTION Test Mode Select. Set this bit to a 1 to force all outputs (including I/O pins) either high (TCR2.6 = 1) or low (TCR2.6 = 0). Test I/O Pins. 0=force all output (and I/O) pins to a logic 0. 1=force all output (and I/O) pins to a logic 1. Transmit Side ZBTSI Enable. 0=ZBTSI disabled. 1=ZBTSI enabled. TSYNC Double-Wide. 0=do not pulse double-wide in signaling frames. 1=do pulse double-wide in signaling frames. (note: this bit must be set to 0 when TCR 2.3 = 1 or when TCR2.2 = 0). TSYNC Mode Select. 0=frame mode (see the timing in Section 13). 1=multiframe mode (see the timing in Section 13). TSYNC I/O Select. 0=TSYNC is an input. 1=TSYNC is an output. Transmit Side D4 Yellow Alarm Select. 0=0s in bit 2 of all channels. 1=a 1 in the S-bit position of frame 12. Bit 7 Zero Suppression Enable. 0=no stuffing occurs. 1=Bit 7 forced to a 1 in channels with all 0s.
TESTIO
TCR2.6
TZBTSI
TCR2.5
TSDW
TCR2.4
TSM
TCR2.3
TSIO
TCR2.2
TD4YM
TCR2.1
B7ZS
TCR2.0
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DS2141A
CCR1: COMMON CONTROL REGISTER 1 (37h)
(MSB) TESE P34F RSAO POSITION CCR1.7 SCLKM RESE PLB (LSB) LLB
SYMBOL TESE
NAME AND DESCRIPTION Transmit Elastic Store Enable. 0=elastic store is bypassed. 1=elastic store is enabled. Function of Pin 34. 0=Receive Loss of Sync (RLOS). 1=Loss of Transmit Clock (LOTC). Receive Signaling All 1's. 0=allow robbed signaling bits to appear at RSER. 1=force all robbed signaling bits at RSER to 1. Not Assigned. Should be set to 0 when written to. SYSCLK Mode Select. 0=if SYSCLK is 1.544 MHz. 1=if SYSCLK is 2.048 MHz. Receive Elastic Store Enable. 0=elastic store is bypassed. 1=elastic store is enabled. Payload Loopback. 0=loopback disabled. 1=loopback enabled. Local Loopback. 0=loopback disabled. 1=loopback enabled.
P34F
CCR1.6
RSAO
CCR1.5
SCLKM
CCR1.4 CCR1.3
RESE
CCR1.2
PLB
CCR1.1
LLB
CCR1.0
PAYLOAD LOOPBACK
When CCR1.1 is set to a 1, the DS2141A will be forced into Payload LoopBack (PLB). Normally, this loopback is only enabled when ESF framing is being performed. In a PLB situation, the DS2141A will loop the 192 bits of payload data (with BPVs corrected) from the receive section back to the transmit section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped back, they are reinserted by the DS2141A. When PLB is enabled, the following will occur: 1. Data will be transmitted from the TPOS and TNEG pins synchronous with RCLK instead of TCLK. 2. All of the receive side signals will continue to operate normally. 3. The TCHCLK and TCHBLK signals are forced low. 4. Data at the TSER pin is ignored. 5. The TLCLK signal will become synchronous with RCLK instead of TCLK. 11 of 39
DS2141A
LOCAL LOOPBACK
When CCR1.0 is set to a 1, the DS2141A will enter a Local LoopBack (LLB) mode. This loopback is useful in testing and debugging applications. In LLB, the DS2141A will loop data from the transmit side back to the receive side. This loopback is synonymous with replacing the RCLK input with the TCLK signal, and the RPOS/RNEG inputs with the TPOS/TNEG outputs. When LLB is enabled, the following will occur: 1. The TPOS and TNEG pins will transmit an unframed all 1's. 2. Data at RPOS and RNEG will be ignored. 3. All receive side signals will take on timing synchronous with TCLK instead of RCLK.
CCR1: COMMON CONTROL REGISTER 2 (38h)
(MSB) TFM TB8ZS TSLC96 POSITION CCR2.7 TFDL RFM RB8ZS RSLC96 (LSB) RFDL
SYMBOL TFM
NAME AND DESCRIPTION Transmit Frame Mode Select. 0=D4 framing mode. 1=ESF framing mode. Transmit B8ZS Enable. 0=B8ZS disabled. 1=B8ZS enabled. Transmit SLC-96/Fs Bit Insertion Enable. 0=SLC-96 disabled. 1=SLC-96 enabled. Transmit Zero Stuffer Enable. 0=zero stuffer disabled. 1=zero stuffer enabled. Receive Frame Mode Select. 0=D4 framing mode. 1=ESF framing mode. Receive B8ZS Enable. 0=B8ZS disabled. 1=B8ZS enabled. Receive SLC-96 Enable. 0=SLC-96 disabled. 1=SLC-96 enabled. Receive Zero Destuffer Enable. 0=zero destuffer disabled. 1=zero destuffer enabled.
TB8ZS
CCR2.6
TSLC96
CCR2.5
TFDL
CCR2.4
RFM
CCR2.3
RB8ZS
CCR2.2
RSLC96
CCR2.1
RFDL
CCR2.0
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DS2141A
4.0 STATUS AND INFORMATION REGISTERS
There is a set of three registers that contain information on the current real time status of the DS2141A: Status Register 1 (SR1), Status Register 2 (SR2), and the Receive Information Register (RIR). When a particular event has occurred (or is occurring), the appropriate bit in one of these three registers will be set to a 1. All of the bits in these registers operate in a latched fashion. This means that if an event occurs and a bit is set to a 1 in any of the registers, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred again (or in the case of RLOS, if loss of sync is still present). The user will always precede a read of these registers with a write. The byte written to the register will inform the DS2141A which bits the user wishes to read and have cleared. The user will write a byte to one of these three registers, with a 1 in the bit positions he or she wishes to read and a 0 in the bit positions he or she does not wish to obtain the latest information on. When a 1 is written to a bit location, the read register will be updated with current value and it will be cleared. When a 0 is written to a bit position, the read register will not be updated and the previous value will be held. A write to the status and information registers will be immediately followed by a read of the same register. The read result should be logically AND'ed with the mask byte that was just written and this value should be written back into the same register to insure that the bit does indeed clear. This second write is necessary because the alarms and events in the status registers occur asynchronously in respect to their access via the parallel port. This scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS2141A with higher-order software languages. The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the INT1 and INT2 pins respectively. Each of the alarms and events in the SR1 and SR2 can be either masked or unmasked from the interrupt pins via the Interrupt Mask Register 1 (IMR1) and Interrupt Mask Register 2 (IMR2) respectively.
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DS2141A
RIR: RECEIVE INFORMATION REGISTER (22h)
(MSB) COFA 8ZD 16ZD POSITION RIR.7 RESF RESE SEFE B8ZS (LSB) FBE
SYMBOL COFA
NAME AND DESCRIPTION Change of Frame Alignment. Set when the last resync resulted in a change of frame or multiframe alignment. Eight Zero Detect. Set when a string of eight consecutive 0s has been received at RPOS and RNEG. Sixteen Zero Detect. Set when a string of 16 consecutive 0s has been received at RPOS and RNEG. Receive Elastic Store Full. Set when the elastic store buffer fills and a frame is deleted. Receive Elastic Store Empty. Set when the elastic store buffer empties and a frame is repeated. Severely Errored Framing Event. Set when 2 out of 6 framing bits are received in error. B8ZS Code Word Detect. Set when a B8ZS code word is detected at RPOS and RNEG independent of whether the B8ZS mode is selected or not via CCR2.2. Frame Bit Error. Set when a Ft (D4) or FPS (ESF) framing bit is received in error.
8ZD
RIR.6
16ZD
RIR.5
RESF
RIR.4
RESE
RIR.3
SEFE
RIR.2
B8ZS
RIR.1
FBE
RIR.0
Note: If the transmit elastic store slips, both RIR.4 and RIR.3 will be set.
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DS2141A
SR1: STATUS REGISTER 1 (20h)
(MSB) LUP LDN LOTC POSITION SR1.7 SLIP RBL RYEL RCL (LSB) RLOS
SYMBOL LUP
NAME AND DESCRIPTION Loop Up Code Detected. Set when the repeating ...00001... loop up code is being received. Loop Down Code Detected. Set when the repeating ...001... loop down code is being received. Loss of Transmit Clock. Set when the TCLK pin has not transitioned for one channel time (or 5.2 s). Will force pin-34 high if enabled via CCR1.6. Based on RCLK. Elastic Store Slip Occurrence. Set when the elastic store has either repeated or deleted a frame of data. Receive Blue Alarm. Set when an all 1's code is received at RPOS and RNEG. Receive Yellow Alarm. Set when a yellow alarm is received at RPOS and RNEG. Receive Carrier Loss. Set when 192 consecutive 0s have been detected at RPOS and RNEG. Receive Loss of Sync. Set when the device is not synchronized to the receive T1 stream.
LDN
SR1.6
LOTC
SR1.5
SLIP
SR1.4
RBL
SR1.3
RYEL
SR1.2
RCL
SR1.1
RLOS
SR1.0
LOOP UP/DOWN CODE DETECTION
Bits SR1.7 and SR1.6 will indicate when either the standard "loop up" or "loop down" codes are being received by the DS2141A. When a loop up code has been received for 5 seconds, the CPE is expected to loop the recovered data (without correcting BPVs) back to the source. The loop down code indicates that the loopback should be discontinued. See the AT&T publication TR 62411 for more details. The DS2141A will detect the loop up/down codes in both framed and unframed circumstances with bit error rates as high as 10-2. The loop code detector has a nominal integration period of 48 ms. Hence, after about 48 ms of receiving either code, the proper status bit will be set to a 1. After this initial indication, it is recommended that the software poll the DS2141A every 100 ms to 500 ms until five seconds have elapsed to insure that the code is continuously present. Once five seconds have passed, the line interface should be taken into or out of loopback.
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DS2141A
SR2: STATUS REGISTER 2 (21h)
(MSB) RMF TMF SEC POSITION SR2.7 SR2.6 SR2.5 RFDL TFDL RMTCH RAF (LSB) LORC
SYMBOL RMF TMF SEC
NAME AND DESCRIPTION Receive Multiframe. Set on receive multiframe boundaries. Transmit Multiframe. Set on transmit multiframe boundaries. One Second Timer. Set on increments of one second based on RCLK; will be set in increments of 999 ms, 999 ms, and 1002 ms every three seconds. Receive FDL Buffer Full. Set when the receive FDL buffer (RFDL) fills to capacity (8-bits). Transmit FDL Buffer Empty. Set when the transmit FDL buffer (TDFL) empties. Receive FDL Match Occurrence. Set when the RFDL matches either RFDLM1 or RFDLM2. Receive FDL Abort. Set when eight consecutive 1's are received in the FDL. Loss of Receive Clock. Set when the RCLK pin has not transitioned for at least 2 s (3 s 1 s).
RFDL
SR2.4
TFDL
SR2.3
RMTCH
SR2.2
RAF
SR2.1
LORC
SR2.0
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DS2141A
IMR1: INTERRUPT MASK REGISTER 1 (7Fh)
(MSB) LUP LDN LOTC POSITION IMR1.7 SLIP RBL RYEL RCL (LSB) RLOS
SYMBOL LUP
NAME AND DESCRIPTION Loop Up Code Detected. 0=interrupt masked. 1=interrupt enabled. Loop Down Code Detected. 0=interrupt masked. 1=interrupt enabled. Loss of Transmit Clock. 0=interrupt masked. 1=interrupt enabled. Elastic Store Slip Occurrence. 0=interrupt masked. 1=interrupt enabled. Receive Blue Alarm. 0=interrupt masked. 1=interrupt enabled. Receive Yellow Alarm. 0=interrupt masked. 1=interrupt enabled. Receive Carrier Loss. 0=interrupt masked. 1=interrupt enabled. Receive Loss of Sync. 0=interrupt masked. 1=interrupt enabled.
LDN
IMR1.6
LOTC
IMR1.5
SLIP
IMR1.4
RBL
IMR1.3
RYEL
IMR1.2
RCL
IMR1.1
RLOS
IMR1.0
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IMR2: INTERRUPT MASK REGISTER 2 (6Fh)
(MSB) RMF TMF SEC POSITION IMR2.7 RFDL TFDL RMTCH RAF (LSB) LORC
SYMBOL RMF
NAME AND DESCRIPTION Receive Multiframe. 0=interrupt masked. 1=interrupt enabled. Transmit Multiframe. 0=interrupt masked. 1=interrupt enabled. One Second Timer. 0=interrupt masked. 1=interrupt enabled. Receive FDL Buffer Full. 0=interrupt masked. 1=interrupt enabled. Transmit FDL Buffer Empty. 0=interrupt masked. 1=interrupt enabled. Receive FDL Match Occurrence. 0=interrupt masked. 1=interrupt enabled. Receive FDL Abort. 0=interrupt masked. 1=interrupt enabled. Loss of Receive Clock. 0=interrupt masked. 1=interrupt enabled.
TMF
IMR2.6
SEC
IMR2.5
RFDL
IMR2.4
TFDL
IMR2.3
RMTCH
IMR2.2
RAF
IMR2.1
LORC
IMR2.0
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5.0 ERROR COUNT REGISTERS
There is a set of three counters in the DS2141A that record bipolar violations, errors in the CRC6 code words, and frame bit errors. Each of these three counters is automatically updated on 1-second boundaries as determined by the 1-second timer in Status Register 2 (SR2.5). Hence, these registers contain performance data from the previous second. The user can use the interrupt from the 1-second timer to determine when to read these registers. The user has a full second to read the counters before the data is lost.
BPVCR1: BIPOLAR VIOLATION COUNT REGISTER 1 (23h) BPVCR2: BIPOLAR VIOLATION COUNT REGISTER 2 (24h)
(MSB) BV15 BV7 BV14 BV6 BV13 BV5 POSITION BPVCR1.7 BPVCR2.0 BV12 BV4 BV11 BV3 BV10 BV2 BV9 BV1 (LSB) BV8 BV0 BPVCR1 BPVCR2
SYMBOL BV15 BV0
NAME AND DESCRIPTION MSB of the bipolar violation count. LSB of the bipolar violation count.
Bipolar Violation Count Register 1 (BPVCR1) is the most significant word and BPVCR2 is the least significant word of a 16-bit counter that records bipolar violations (BPVs). If the B8ZS mode is set for the receive side via CCR2.2, then B8ZS code words are not counted. This counter increments at all times and is not disabled by loss of sync conditions. The counter saturates at 65,535 and will not roll over. If the DS2141A is programmed to record ESF error events (RCR2.0=1), then the BPVCR will increment for each ESF multiframe that contains either an error in the CRC6 word or an out-of-frame occurrence (loss of sync).
CRCCR1: CRC6 COUNT REGISTER 1 (25h) CRCCR2: CRC6 COUNT REGISTER 2 (26h)
(MSB) CRC7 CRC7 CRC6 CRC6 CRC5 CRC5 POSITION CRCCR1.7 CRCCR2.0 CRC4 CRC4 CRC3 CRC3 CRC2 CRC2 CRC1 CRC1 (LSB) CRC0 CRC0 CRCCR1 CRCCR2
SYMBOL CRC7 CRC0
NAME AND DESCRIPTION MSB of the CRC6 count. LSB of the CRC6 count.
CRC6 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant word of a 16-bit counter that records word errors in the Cyclic Redundancy Check 6 (CRC6) when the DS2141A is operated in the ESF framing mode (CCR2.3 = 1). This counter saturates at 65,535 and will not roll over. The counter is disabled during loss of sync conditions.
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FECR: FRAME ERROR COUNT REGISTER (27h)
(MSB) FE7 FE6 FE5 POSITION FECR.7 FECR.0 FE4 FE3 FE2 FE1 (LSB) FE0
SYMBOL FE7 FE0
NAME AND DESCRIPTION MSB of the Frame Error count. LSB of the Frame Error count.
The Frame Error Count Register (FECR) is a 8-bit counter that records either errors in the framing pattern. The FECR will count individual bit errors in the ESF framing pattern (...001011...) if the device is set into the ESF framing mode (CCR2.3 = 1) and it will count individual bit errors in the Ft framing pattern (...101010...) in the D4 framing mode (CCR2.3 = 0). If RCR2.1=1, then the FECR will also record individual bit errors in the Fs framing pattern (...001110...) when it is in the D4 framing mode. This counter saturates at 255 and will not roll over. The counter is disabled during loss of sync conditions.
6.0 FDL/FS EXTRACTION AND INSERTION
The DS2141A has the ability to extract/insert data from/into the Facility Data Link (FDL) in the ESF framing mode and from/into Fs-bit position in the D4 framing mode. Since SLC-96 utilizes the Fs-bit position, this capability can also be used in SLC-96 applications. The operation of the receive and transmit sections will be discussed separately.
6.1 Receive Section
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2 ms (8 x 250 s). The DS2141A will signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled via IMR2.4, the INT2 pin will toggle low indicating that the buffer has filled and needs to be read. The user has 2 ms to read this data before it is lost. If the byte in the RFDL matches either of the bytes programmed into the RFDLM1 or RFDLM2 registers, then the SR2.2 bit will be set to a 1 and the INT2 pin will toggled low if enabled via IMR2.2. This feature allows an external microcontroller to ignore the FDL or Fs pattern until an important event occurs. The DS2141A also contains a 0 destuffer which is controlled via the CCR2.0 bit. In both ANSI T1.403 and TR54016, communications on the FDL follow a subset of a LAPD protocol. The LAPD protocol states that no more than five 1's should be transmitted in a row so that the data does not resemble an opening or closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.0, the DS2141A will automatically look for five 1's in a row, followed by a 0. If it finds such a pattern, it will automatically remove the 0. If the 0 destuffer sees six or more 1's in a row followed by a 0, the 0 is not removed. The CCR2.0 bit should always be set to a 1 when the DS2141A is extracting the FDL. More on how to use the DS2141A in FDL applications is covered in a separate Application Note.
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RFDL: RECEIVE FDL REGISTER (28h)
(MSB) RFDL7 RFDL6 RFDL5 POSITION RFDL.7 RFDL.0 RFDL4 RFDL3 RFDL2 RFDL1 (LSB) RFDL0
SYMBOL RFDL7 RFDL0
NAME AND DESCRIPTION MSB of the Received FDL Code. LSB of the Received FDL Code.
The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fsbits. The LSB is received first.
RFDLM1: RECEIVE FDL MATCH REGISTER 1 (29h) RFDLM2: RECEIVE FDL MATCH REGISTER 2 (2Ah)
(MSB) RFDL7 RFDL6 RFDL5 POSITION RFDL.7 RFDL.0 RFDL4 RFDL3 RFDL2 RFDL1 (LSB) RFDL0
SYMBOL RFDL7 RFDL0
NAME AND DESCRIPTION MSB of the FDL Match Code. LSB of the FDL Match Code.
When the byte in the Receive FDL Register matches either of the two Receive FDL Match Registers (RFDLM1/RFDLM2), RSR2.2 will be set to a 1 and the INT2 will go active if enabled via IMR2.2.
6.2 Transmit Section
The transmit section will shift out either the FDL (in the ESF framing mode) or the Fs-bits (in the D4 framing mode) contained in the Transmit FDL register (TFDL) into the T1 data stream. When a new value is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing T1 data stream. After the full 8 bits have been shifted out, the DS2141A will signal the host microcontroller that the buffer is empty and that more data is needed by setting the SR2.3 bit to a 1. The INT2 will also toggle low if enabled via IMR2.3. The user has 2 ms (1.5 ms in SLC-96 applications) to update the TFDL with a new value. If the TFDL is not updated, the old value in the TFDL will be transmitted once again. The DS2141A also contains a 0 stuffer which is controlled via the CCR2.4 bit. In both ANSI T1.403 and TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states that no more than five 1's should be transmitted in a row so that the data does not resemble an opening or closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.4, the DS2141A will automatically look for five 1's in a row. If it finds such a pattern, it will automatically insert a 0 after the five 1's. The CCR2.0 bit should always be set to a 1 when the DS2141A is inserting the FDL. More on how to use the DS2141A in FDL applications is covered in a separate Application Note.
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TFDL: TRANSMIT FDL REGISTER (7Eh)
(MSB) TFDL7 TFDL6 TFDL5 POSITION TFDL.7 TFDL.0 TFDL4 TFDL3 TFDL2 TFDL1 (LSB) TFDL0
SYMBOL TFDL7 TFDL0
NAME AND DESCRIPTION MSB of the FDL code to be transmitted. LSB of the FDL code to be transmitted.
The Transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first.
7.0 SIGNALING OPERATION
The robbed bit signaling bits in embedded in the T1 stream can be extracted from the receive stream and inserted into the transmit stream by the DS2141A. There is a set of 12 registers for the receive side (RS1 to RS12) and 12 registers on the transmit side (TS1 to TS12). The signaling registers are detailed below. The CCR1.5 bit is used to control the robbed signaling bits as they appear at RSER. If CCR1.5 is set to 0, then the robbed signaling bits will appear at RSER in their proper position as they are received. If CCR1.5 is set to a 1, then the robbed signaling bit positions will be forced to a 1 at RSER.
RS1 TO RS12: RECEIVE SIGNALING REGISTERS (60h to 6Bh)
(MSB) A(8) A(16) A(24) B(8) B(16) B(24) C(8) C(16) C(24) D(8) D(16) D(24) A(7) A(15) A(23) B(7) B(15) B(23) C(7) C(15) C(23) D(7) D(15) D(23) A(6) A(14) A(22) B(6) B(14) B(22) C(6) C(14) C(22) D(6) D(14) D(22) POSITION RS12.7 RS1.0 A(5) A(13) A(21) B(5) B(13) B(21) C(5) C(13) C(21) D(5) D(13) D(21) A(4) A(12) A(20) B(4) B(12) B(20) C(4) C(12) C(20) D(4) D(12) D(20) A(3) A(11) A(19) B(3) B(11) B(19) C(3) C(11) C(19) D(3) D(11) D(19) A(2) A(10) A(18) B(2) B(10) B(18) C(2) C(10) C(18) D(2) D(10) D(18) (LSB) A(1) RS1 (60) A(9) RS2 (61) A(17) RS3 (62) B(1) RS4 (63) B(9) RS5 (64) B(17) RS6 (65) C(1) RS7 (66) C(9) RS8 (67) C(17) RS9 (68) D(1) RS10 (69) D(9) RS11 (6A) D(17) RS12 (6B)
SYMBOL D(24) A(1)
NAME AND DESCRIPTION Signaling Bit D in Channel 24. Signaling Bit A in Channel 1.
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Each Receive Signaling Register (RS1 to RS12) reports the incoming robbed bit signaling from eight DS0 channels. In the ESF framing mode, there can be up to 4 signaling bits per channel (A, B, C, and D). In the D4 framing mode, there are only 2 framing bits per channel (A and B). In the D4 framing mode, the DS2141A will replace the C and D signaling bit positions with the A and B signaling bits from the previous multiframe. Hence, whether the DS2141A is operated in either framing mode, the user needs only to retrieve the signaling bits every 3 ms. The bits in the Receive Signaling Registers are updated on multiframe boundaries so the user can utilize the Receive Multiframe Interrupt in the Receive Status Register 2 (SR2.7) to know when to retrieve the signaling bits. The Receive Signaling Registers are frozen and not updated during a loss of sync condition (SR1.0=1). They will contain the most recent signaling information before the "OOF" occurred.
TS1 TO TS12: TRANSMIT SIGNALING REGISTERS (70h to 7Bh)
(MSB) A(8) A(16) A(24) B(8) B(16) B(24) C(8) C(16) C(24) D(8) D(16) D(24) A(7) A(15) A(23) B(7) B(15) B(23) C(7) C(15) C(23) D(7) D(15) D(23) A(6) A(14) A(22) B(6) B(14) B(22) C(6) C(14) C(22) D(6) D(14) D(22) POSITION TS12.7 TS1.0 A(5) A(13) A(21) B(5) B(13) B(21) C(5) C(13) C(21) D(5) D(13) D(21) A(4) A(12) A(20) B(4) B(12) B(20) C(4) C(12) C(20) D(4) D(12) D(20) A(3) A(11) A(19) B(3) B(11) B(19) C(3) C(11) C(19) D(3) D(11) D(19) A(2) A(10) A(18) B(2) B(10) B(18) C(2) C(10) C(18) D(2) D(10) D(18) (LSB) A(1) TS1 (70) A(9) TS2 (71) A(17) TS3 (72) B(1) TS4 (73) B(9) TS5 (74) B(17) TS6 (75) C(1) TS7 (76) C(9) TS8 (77) C(17) TS9 (78) D(1) TS10 (79) D(9) TS11 (7A) D(17) TS12 (7B)
SYMBOL D(24) A(1)
NAME AND DESCRIPTION Signaling Bit D in Channel 24. Signaling Bit A in Channel 1.
Each Transmit Signaling Register (TS1 to TS12) contains the Robbed Bit signaling for eight DS0 channels that will be inserted into the outgoing stream if enabled to do so via TCR1.4. In the ESF framing mode, there can be up to 4 signaling bits per channel (A, B, C, and D). In the D4 framing mode, there are only 2 framing bits per channel (A and B). On multiframe boundaries, the DS2141A will load the values present in the Transmit Signaling Register into an outgoing signaling shift register that is internal to the device. The user can utilize the Transmit Multiframe Interrupt in Status Register 2 (SR2.6) to know when to update the signaling bits.
8.0 SPECIAL TRANSMIT SIDE REGISTERS
There is a set of seven registers in the DS2141A that can be used to custom tailor the data that is to be transmitted onto the T1 line, on a channel by channel basis. Each of the 24 T1 channels can be either forced to be transparent or to have a user defined idle code inserted into them. Each of these special registers is defined below.
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TTR1/TTR2/TTR3: TRANSMIT TRANSPARENCY REGISTERS (39h to 3Bh)
(MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 POSITION TTR3.7 TTR1.0 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 TTR1 (39) CH9 TTR2 (3A) CH17 TTR3 (3B)
SYMBOL CH24 CH1
NAME AND DESCRIPTION Transmit Transparency Registers. 0=this DS0 channel is not transparent. 1=this DS0 channel is transparent.
Each of the bit positions in the Transmit Transparency Registers (TTR1/TTR2/TTR3) represents a DS0 channel in the outgoing frame. When these bits are set to a 1, the corresponding channel is transparent (or clear). If a DS0 is programmed to be clear, no robbed bit signaling will be inserted nor will the channel have bit 7 stuffing performed. However, in the D4 framing mode, bit 2 will be overwritten by a 0 when a Yellow Alarm is transmitted.
TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (3Ch to 3Eh)
(MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 POSITION TTR3.7 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 TIR1 (3C) CH9 TIR2 (3D) CH17 TIR3 (3E)
SYMBOL CH24
NAME AND DESCRIPTION Transmit Idle Registers. 0=do not insert the Idle Code into this DS0 channel. 1=insert the Idle Code into this channel.
CH1
TTR1.0
TIDR: TRANSMIT IDLE DEFINITION REGISTER (3Fh)
(MSB) TIDR7 TIDR6 TIDR5 POSITION TIDR.7 TIDR.0 TIDR4 TIDR3 TIDR2 TIDR1 (LSB) TIDR0
SYMBOL TIDR7 TIDR0
NAME AND DESCRIPTION MSB of the Idle Code. LSB of the Idle Code.
Each of the bit positions in the Transmit Idle Registers (TIR1/TIR2/TIR3) represents a DS0 channel in the outgoing frame. When these bits are set to a 1, the corresponding channel will transmit the Idle Code contained in the Transmit Idle Definition Register (TIDR). Robbed bit signaling and bit 7 stuffing will occur over the programmed Idle Code unless the DS0 channel is made transparent by the Transmit Transparency Registers.
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9.0 CLOCK BLOCKING REGISTERS
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins respectively. The RCHBLK and TCHCLK pins are user-programmable outputs that can be forced either high or low during individual channels. These outputs can be used to block clocks to a USART or LAPD controller in Fractional T1, E1 to T1, or ISDN-PRI applications. When the appropriate bits are set to a 1, the RCHBLK and TCHCLK pins will be held high during the entire corresponding channel time. See the timing in Section 13 for an example.
RCBR1/RCBR2/RCBR3: RECEIVE CHANNEL BLOCKING REGISTERS (6Ch to 6Eh)
(MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 POSITION RCBR3.7 RCBR1.0 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 RCBR1 (6C) CH9 RCBR2 (6D) CH17 RCBR3 (6E)
SYMBOL CH24 CH1
NAME AND DESCRIPTION Receive Channel Blocking Registers. 0=force the RCHBLK pin to remain low during this channel time. 1=force the RCHBLK pin high during this channel time.
TCBR1/TCBR2/TCBR3: TRANSMIT CHANNEL BLOCKING REGISTERS (32h to 34h)
(MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 POSITION RCBR3.7 RCBR1.0 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 TCBR1 (32) CH9 TCBR2 (33) CH17 TCBR3 (34)
SYMBOL CH24 CH1
NAME AND DESCRIPTION Transmit Channel Blocking Registers. 0=force the TCHBLK pin to remain low during this channel time. 1=force the TCHBLK pin high during this channel time.
10.0 ELASTIC STORES OPERATION
The DS2141A has two onboard two-frame (386 bits) elastic stores. These elastic stores have two main purposes. First, they can be used to rate convert the T1 data stream to 2.048 Mbps (or a multiple of 2.048 Mbps) which is the E1 rate. Secondly, they can be used to absorb the differences in frequency and phase between the T1 data stream and an asynchronous (i.e., not frequency locked) backplane clock. Both elastic stores contain full controlled slip capability which is necessary for this second purpose. The receive side elastic store can be enabled via CCR1.2 and the transmit side elastic store is enabled via CCR1.7.
10.1 Receive Side
If the receive side elastic store is enabled (CCR1.2 = 1), then the user must provide either a 1.544 MHz (CCR1.3 = 0) or 2.048 MHz (CCR1.3 = 1) clock at the SYSCLK pin. The user has the option of either providing a frame sync at the RFSYNC pin (RCR2.3 = 1) or having the RFSYNC pin provide a pulse on 25 of 39
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frame boundaries (RCR2.3 = 0). If the user wishes to obtain pulses at the frame boundary, then RCR2.4 must be set to 0; if the user wishes to have pulses occur at the multiframe boundary, then RCR2.4 must be set to 1. If the user selects to apply a 2.048 MHz clock to the SYSCLK pin, then the data output at RSER will be forced to all 1's every fourth channel and the F-bit will be deleted. Hence channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be forced to a 1. Also, in 2.048 MHz applications, the RCHBLK output will be forced high during the same channels as the RSER pin. See Section 13 for more details. This is useful in T1 to CEPT (E1) conversion applications. If the 386-bit elastic buffer either fills or empties, a controlled slip will occur. If the buffer empties, then a full frame of data (193 bits) will be repeated at RSER and the SR1.4 and RIR.3 bits will be set to a 1. If the buffer fills, then a full frame of data will be deleted and the SR1.4 and RIR.4 bits will be set to a 1.
10.2 Transmit Side
The transmit side elastic store can only be used if the receive side elastic store is enabled. The operation of the transmit elastic store is very similar to the receive side; both have controlled slip operation and both can operate with either a 1.544 MHz or a 2.048 MHz SYSCLK. When the transmit elastic store is enabled, both the SYSCLK and RSYNC signals are shared by both the elastic stores. Hence, they will have the same backplane PCM frame and data structure. Controlled slips in the transmit elastic store are reported in by setting both RIR.3 and RIR.4.
11.0 RECEIVE MARK REGISTERS
The DS2141A has the ability to replace the incoming data, on a channel-by-channel basis, with either an idle code (7F Hex) or the digital milliwatt code, which is an 8-byte repeating pattern that represents a 1 kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). The RCR2.7-bit will determine which code is used. Each bit in the RMRs represents a particular channel. If a bit is set to a 1, then the receive data in that channel will be replaced with one of the two codes. If a bit is set to 0, no replacement occurs.
RMR1/RMR2/RMR3: RECEIVE MARK REGISTERS (2Dh to 2Fh)
(MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 POSITION RMR3.7 RMR1.0 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 RMR1 (2D) CH9 RMR2 (2E) CH17 RMR3 (2F)
SYMBOL CH24 CH1
NAME AND DESCRIPTION Receive Mark Registers. 0=do not affect the receive data associated with this channel. 1=replace the receive data associated with this channel with either the idle code or the digital milliwatt code.
12.0 LINE INTERFACE CONTROL FUNCTION
The DS2141A can control line interface units that contain serial ports. When Control Register Bytes 1 or 2 (CRB1, CRB2) are written to, the DS2141A will automatically write this data serially (LSB first) into the line interface by creating a chip select, serial clock and serial data via the LI_CS , LI_SCLK and LI_SDI pins respectively. This control function is driven off of the RCLK; therefore RCLK must be present for proper operation. Registers CRB1 and CRB2 can only be written to, not read from. Writes to these registers must be at least 20 sec apart. See Section 13 for timing information.
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CRB1: CONTROL REGISTER BYTE 1 (7Ch) CRB2: CONTROL REGISTER BYTE 2 (7Dh)
(MSB) CR7 CR7 CR6 CR6 SYMBOL CR0 CR7 CR5 CR5 POSITION CRB1.0 CRB2.7 CR4 CR4 CR3 CR3 CR2 CR2 CR1 CR1 (LSB) CR0 CRB1 (7C) CR0 CRB2 (7D)
NAME AND DESCRIPTION LSB of Control Register Byte 1. MSB of Control Register Byte 2.
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13.0 TIMING DIAGRAMS RECEIVE SIDE D4 TIMING
NOTES:
1. RSYNC in the frame mode (RCR2.4=0) and double-wide frame sync is not enabled (RCR2.5=0). 2. RSYNC in the frame mode (RCR2.4=0) and double-wide frame sync is enabled (RCR2.5=1). 3. RSYNC in the multiframe mode (RCR2.4=1). 4. RLINK data (S-bit) is updated 1 bit prior to even frames and held for two frames.
RECEIVE SIDE ESF TIMING
NOTES:
1. RSYNC in the frame mode (RCR2.4=0) and double-wide frame sync is not enabled (RCR2.5=0). 2. RSYNC in the frame mode (RCR2.4=0) and double-wide frame sync is enabled (RCR2.5=1). 3. RSYNC in the multiframe mode (RCR2.4=1). 4. ZBTSI mode disabled (RCR2.6=0). 5. RLINK data (FDL bits) is updated 1 bit time before odd frames and held for two frames. 6. ZBTSI mode is enabled (RCR2.6=1). 7. RLINK data (Z bits) is updated 1 bit time before odd frame and held for four frames.
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1.544 MHz BOUNDARY TIMING (WITH ELASTIC STORE(S) ENABLED)
NOTES:
1. RSYNC is in the output mode (RCR2.3=0). 2. RSYNC is in the input mode (RCR2.3=1). 3. RCHBLK is programmed to block channel 24.
2.048 MHz BOUNDARY TIMING (WITH ELASTIC STORE(S) ENABLED)
NOTES:
1. RSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to 1; TSER data in these channels will be ignored. 2. RSYNC is in the output mode (RCR2.3=0). 3. RSYNC is in the input mode (RCR2.3=1). 4. RCHBLK is forced to 1 in the same channels as RSER (see Note 1).
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RECEIVE SIDE BOUNDARY TIMING (WITH ELASTIC STORE(S) DISABLED)
NOTES:
1. There is a 13 RCLK delay from RPOS, RNEG to RSER. 2. RCHBLK is programmed to block Channel 24.
TRANSMIT SIDE D4 TIMING
NOTES:
1. TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is not enabled (TCR2.4=0). 2. TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is enabled (TCR2.4=1). 3. TSYNC in the multiframe mode (TCR2.3=1). 4. TLINK data (S-bit) is sampled during the F-bit position of even frames for insertion into the outgoing T1 stream when enabled via TCR1.2.
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TRANSMIT SIDE ESF TIMING
NOTES:
1. TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is not enabled (TCR2.4=0). 2. TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is enabled (TCR2.4=1). 3. TSYNC in the multiframe mode (TCR2.4=1). 4. ZBTSI mode disabled (TCR2.5=0). 5. TLINK data (FDL bits) is sampled during the F-bit time of odd frame and inserted into the outgoing T1 stream if enabled via TCR1.2. 6. ZBTSI mode is enabled (TCR2.5=1). 7. TLINK data (Z bits) is sampled during the F-bit time of frame 1, 5, 9, 13, 17, and 21 and inserted into the outgoing stream if enabled via TCR1.2.
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TRANSMIT SIDE BOUNDARY TIMING (WITH ELASTIC STORE(S) DISABLED)
NOTES:
1. There is a 10 TCLK delay from TSER to TPOS, TNEG. 2. TSYNC is in the input mode (TCR2.2=0). 3. TSYNC is in the output mode (TCR2.2=1). 4. TCHBLK is programmed to block Channel 1.
LINE INTERFACE CONTROL TIMING
NOTES:
1. A write to CRB1 will cause the DS2141A to output this sequence. 2. A write to CRB2 will cause the DS2141A to output this sequence. 3. Timing numbers are based on RCLK=1.544 MHz with 50% duty cycle.
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DS2141A
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature * -1.0V to +7.0V 0C to 70C -55C to +125C 260C for 10 seconds
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATION CONDITIONS
PARAMETER Logic 1 Logic 0 Supply SYMBOL VIH VIL VDD MIN 2.0 -0.3 4.5 TYP MAX VDD+0.3 +0.8 5.5
(0C to 70C)
UNITS V V V NOTES
CAPACITANCE
PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN TYP 5 7 MAX UNITS pF pF NOTES
DC CHARACTERISTICS
PARAMETER Supply Current Input Leakage Output Leakage Output Current (2.4V) Output Current (0.4V) SYMBOL IDD IIL ILO IOH IOL MIN -1.0 -1.0 +4.0
(0C to 70C; VDD = 5V + 10%)
TYP 10 MAX +1.0 1.0 UNITS mA A A mA mA NOTES 1 2 3
NOTES:
1. RCLK = TCLK = 1.544 MHz; VDD = 5.5V. 2. 0.0V < VIN < VDD. 3. Applies to INT1 and INT2 when 3-stated.
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DS2141A
AC CHARACTERISTICS - PARALLEL PORT
PARAMETER Cycle Time Pulse Width, DS Low or RD High Pulse Width, DS High or RD Low Input Rise/Fall Times R/ W Hold Time R/ W Setup Time Before DS High CS Setup Time Before DS, WR or RD active CS Hold Time Read Data Hold Time Write Data Hold Time Muxed Address Valid to AS or ALE Fall Muxed Address Hold Time Delay Time, DS, WR or RD to AS or ALE Rise Pulse Width AS or ALE High Delay Time, AS or ALE to DS, WR or RD Output Data Delay Time from DS or RD Data Setup Time SYMBOL tCYC PWEL PWEH tR, tF tRWH tRWS tCS tCH tDHR tDHW tASL tAHL tASD PWASH tASED tDDR tDSW
(0C to 70C; VDD = 5V + 10%)
MIN 250 150 100 10 50 20 0 10 0 20 10 25 40 20 20 80 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES
30
50
100
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DS2141A
INTEL READ AC TIMING
INTEL WRITE AC TIMING
MOTOROLA AC TIMING
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DS2141A
AC CHARACTERISTICS - RECEIVE SIDE
PARAMETER RCLK and SYSCLK Period RCLK and SYSCLK Pulse Width RPOS, RNEG, Setup to RCLK Falling RPOS, RNEG, Hold from RCLK Falling RCLK Rise/Fall Times Data Delay RSYNC Setup to SYSCLK Falling RSYNC Pulse Width SYMBOL tP tCH tCL tSU tHD tR , t F tDD tSU tPW
(0C to 70C; VDD = 5V =10%)
MIN 50 50 25 25 25 120 tCH-5 TYP MAX 648 UNITS ns ns ns ns ns ns ns ns ns NOTES
25 50
RECEIVE SIDE AC TIMING
NOTES:
1. RSYNC is in the output mode (RCR2.3=0). 2. RSYNC is in the input mode (RCR2.3=1).
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DS2141A
AC CHARACTERISTICS - TRANSMIT SIDE
PARAMETER TCLK Period TCLK Pulse Width TSER, TSYNC, TLINK Setup to TCLK Falling TSER, TLINK Hold from TCLK Falling TCLK Rise/Fall Times Data Delay TSYNC Pulse Width SYMBOL tP tCH tCL tSU tHD t R , tF tDD tPW
(0C to 70C; VDD = 5V + 10%)
MIN 50 50 25 25 25 75 50 TYP MAX 648 UNITS ns ns ns ns ns ns ns ns NOTES
TRANSMIT SIDE AC TIMING
NOTES:
1. TSYNC is in the output mode (TCR2.2=1). 2. TSYNC is in the input mode (TCR2.2=0).
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DS2141A
DS2141A T1 CONTROLLER (600-MIL) 40-PIN DIP
DIM A B C D E F G H J K
INCHES MIN MAX 2.040 2.070 0.530 0.560 0.145 0.155 0.600 0.625 0.015 0.040 0.120 0.140 0.090 0.110 0.625 0.675 0.008 0.012 0.015 0.022
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DS2141A
DS2141AQ T1 CONTROLLER 44-PIN PLCC
NOTE1: PIN 1 IDENTIFIER TO BE LOCATED IN ZONE INDICATED.
DIM A A1 A2 B B1 C CH1 D D1 D2 E E1 E2 e1 N
INCHES MIN MAX 0.165 0.180 0.090 0.120 0.020 0.026 0.033 0.013 0.021 0.009 0.012 0.042 0.048 0.685 0.695 0.650 0.656 0.590 0.630 0.685 0.695 0.650 0.656 0.590 0.630 0.050 BSC 44 -
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